View CY28342OCT_4729412.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

high-performance sis645/650 pentium? 4-clock synthesize r cy28342 rev 1.0, november 20, 2006 page 1 of 21 2200 laurelwood road, santa clara, ca 95054 tel: (408) 855-0555 fax:(408) 855-0550 www.spectralinear.com features ? supports pentium 4-type cpus 3.3v power supply eight copies of pci clocks one 48 mhz usb clock two copies of zclk clocks one 48 mhz/24mhz programmable sio clock two differential cpu clock pairs smbus support with read-back capabilities spread spectrum emi reduction dial-a-frequency ? features dial-a-ratio? features dial-a-db ? features 48-pin ssop and tssop packages watchdog function note: 1. pins marked with [*] have internal pull-up resistors. pins marked with [**] have internal pull-down resistors. block diagram pin configuration [1] pll1 pll2 /2 wd logic xin xout cpu_stp# iref fs(0:4) mult0 vttpwrgd pci_stp# pd# sdata sclk 48m_24m# 48m pci_f(0:1) pci(0:5) zclk(0:1) agp(0:1) cpu(0:1)c cpu(0:1)t ref(0:2) i2c logic sreset# power on latch sdclk 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 vddsd sdclk vsssd cpu_stp#* cpu1t cpu1c vddc vssc cpu0t cpu0c iref vssa vdda sclk sdata pd#/vttpwrgd* vssagp agp0 agp1 vddagp vdd48m 48m 24_48m/mult0* vss48m vddr **fs0/ref0 **fs1/ref1 **fs2/ref2 vssr xin xout vssz zclk0 zclk1 vddz *sreset#/pci_stp# vddp **fs3/pci_f0 pci0 **fs4/pci_f1 pci1 vssp vddp pci2 pci3 pci4 pci5 vssp cy28342 48 pin ssop andf tssop
cy28342 rev 1.0, november 20, 2006 page 2 of 21 table 1. frequency table fs(4:0) cpu (mhz) sdram (mhz) zclk (mhz) agp (mhz) pci (mhz) vco (mhz) 00000 100.20 100.20 66.80 66.80 33.40 400.8 00001 133.45 133.45 66.73 66.73 33.365 533.8 00010 100.20 133.60 66.80 66.80 33.40 400.8 00011 133.45 100.09 66.73 66.73 33.365 400.4 00100 100.20 167.00 62.63 62.63 31.315 501.0 00101 133.33 166.66 66.67 66.67 33.335 666.7 00110 100.20 150.30 66.80 66.80 33.40 601.2 00111 133.33 66.67 66.67 66.67 33.335 533.3 01000 100.20 120.24 66.80 66.80 33.40 601.2 01001 145.00 145.00 64.44 64.44 32.22 580.0 01010 111.11 133.33 66.67 66.67 33.335 666.7 01011 166.60 133.28 66.64 66.64 32.22 666.4 01100 66.80 66.80 66.80 66.80 33.40 400.8 01101 66.80 66.80 50.10 50.10 25.05 400.8 01110 100.20 133.60 100.20 66.80 33.40 400.8 01111 100.20 133.60 80.16 66.80 33.40 400.8 10000 100.20 167.00 83.50 62.63 31.315 501.0 10001 100.20 167.00 100.20 62.63 31.315 501.0 10010 102.20 136.27 68.13 68.13 34.065 408.8 10011 133.40 200.10 66.70 66.70 33.35 400.2 10100 105.00 140.00 70.00 70.00 35.00 420.0 10101 83.33 138.89 69.44 69.44 34.72 416.6 10110 108.00 144.00 72.00 72.00 36.00 432.0 10111 83.33 104.16 69.44 69.44 34.72 416.6 11000 116.00 145.00 64.44 64.44 32.22 580.0 11001 83.33 166.67 62.50 62.50 31.25 500.0 11010 120.00 150.00 66.67 66.67 33.335 600.0 11011 95.00 142.50 63.33 63.33 31.665 570.0 11100 112.00 140.00 62.22 62.22 31.11 560.0 11101 75.00 125.00 62.50 62.50 31.25 375.0 11110 108.00 180.00 67.50 67.50 33.75 540.0 11111 95.00 158.33 79.17 79.17 39.585 475.0
cy28342 rev 1.0, november 20, 2006 page 3 of 21 pin description [2] pin name pwr i/o description 6xin i oscillator buffer input . connect to a crystal or to an external clock. 7 xout vddr o oscillator buffer output . connect to a crystal . do not connect when an external clock is applied at xin. 39,40,43,44 cpu (0:1)t, cpu (0:1)c vddc o differential host ou tput clock pairs . see ta ble 1 for frequencies and functionality. 16,17,20,23 pci (0:5) vddp o pci clock outputs . see table 1 . 14 fs3/pci_f0 vddp i/o pd power-on bidirectional input/output (i/o) . at power-up, fs3 is the input. when vttpwrgd transitions to a logic high, fs3 state is latched and this pin becomes pci_f0 clock output. see table 1 . 15 fs4/pci_f1 vddp i/o pd power-on bidirectional i/o . at power-up, fs4 is the input. when vttpwrgd transitions to a logic high, fs4 state is latched and this pin becomes pci_f1 clock output. see table 1 . 2 fs0/ref0 vddr i/o pd power-on bidirectional i/o . at power-up, fs0 is the input. when vttpwrgd transitions to a logic high, fs0 state is latched and this pin becomes ref0, buffered output copy of the device?s xin clock. 3 fs1/ref1 vddr i/o pd power-on bidirectional i/o . at power-up, fs1 is the input. when vttpwrgd is transited to logic low, fs1 state is latched and this pin becomes ref1, buffered output copy of the device?s xin clock. 4 fs2/ref2 vddr i/o pd power-on bidirectional i/o . at power-up, fs2 is the input. when vttpwrgd is transited to logic low, fs2 state is latched and this pin becomes ref2, buffered output copy of the device?s xin clock. 38 iref i current reference programming input for cpu buffers . a resistor is connected between this pin and v ss . see figure 8 . 33 pd#/vttpr gd i pu power-down input/vtt power good input . at power-up, vttpwrgd is the input. when this input is transitions initially from low to high, the fs (0:4) and mult0 are latched. after the first low-to-high transition, this pin becomes a pd# input with an internal pull-up. when pd# is asserted low, the device enters power-down mode. see power management function. 27 48m vdd48m o fixed 48-mhz usb clock output . 26 24_48m/mul t0 vdd48m i/o pu power-on bidirectional i/o . at power-up, mult0 is the input. when vttpwrgd is transitions to logic high mult0 state is latched and this pin becomes 24_48m, sio programmable clock output. 9,10 zclk (0:1) vddz o hyperzip clock outputs . see table 1 . 34 sdata i/o serial data input . conforms to the smbus specification of a slave receive/transmit device. it is an input when receiving data, and an open drain output when acknowledging or transmitting data. 35 sclk i serial clock input . conforms to the smbus specification. 12 sreset# o pci clock disable input . if byte12 bit7 = 0, this pin becomes an sreset# open drain output, and the internal pull-up is not active. see system reset description. pci_stp# i pu system reset control output . if byte12 bit7 = 1 (default), this pin becomes pci clock disable input. when pci_stp# is asserted low, pci (0:5) clocks are synchronously disabled in a low state. this pin does not affect pci_f (0:1) if they are programmed to be free-running clocks via the device?s smbus interface. 45 cpu_stp# i pu cpu clock disable input . when asserted low, cpu (0:1)t clocks are synchronously disabled in a high state and cpu (0:1)c clocks are synchronously disabled in a low state.
cy28342 rev 1.0, november 20, 2006 page 4 of 21 serial data interface to enhance the flexibility and function of the clock synthesizer, a two-signal serial interface is provided. through the serial data interface (sdi), various device functions such as individual clock output buffers, etc., can be individually enabled or disabled. the registers associated with the sdi initializes to their default setting upon power-up, and therefore the use of this interface is optional. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. data protocol the clock driver serial protocol accepts byte write, byte read, block write, and block read operations from the controller. for a block write/read operation, the bytes must be accessed in sequential order from lowest to highest byte (most significant bit first) with the ability to stop after any complete byte has been transferred. for byte write and byte read operations, the system controller can access individual indexed bytes. the offset of the indexed byte is encoded in the command code, as described in table 2 . the block write and block read protocol is outlined in table 3 while ta ble 4 outlines the corresponding byte write and byte read protocol. the slave receiver address is 11010010 (d2h). note: 2. pu = internal pull-up. pd = internal pull-down. t = tri-level logic input with valid logic voltages of low = < 0.8v, t = 1.0 ?1.8v, and high = > 2.0v. 47 sdclk vddsd o sdram clock output . 30,31 agp (0:1) vddagp o agp clock outputs . see ta ble 1 for frequencies and functionality. 48 vddsd pwr 3.3v power supply for sdram clock output. 29 vddagp pwr 3.3v power supply for agp clock output. 11 vddz pwr 3.3v power supply for hyperzip clock output. 1 vddr pwr 3.3v power supply for ref clock output. 13,19 vddp pwr 3.3v power supply for pci clock output. 42 vddc pwr 3.3v power supply for cpu clock output. 28 vdd48m pwr 3.3v power supply for 48-mhz/24-mhz clock output. 36 vdda pwr 3.3v analog power supply. 18,24 vssp pwr gnd for pci clocks outputs. 41 vssc pwr gnd for cpu clocks outputs. 8 vssz pwr gnd for hyperzip clocks outputs. 25 vss48m pwr gnd for 48-mhz/24-mhz clocks outputs. 5 vssr pwr gnd for ref clocks outputs. 46 vsssd pwr gnd for sdram clocks outputs. 32 vssagp pwr gnd for agp clocks outputs. 37 vssa pwr gnd for analog. pin description (continued) [2] pin name pwr i/o description
cy28342 rev 1.0, november 20, 2006 page 5 of 21 table 2. command code definition bit description 7 0 = block read or block write operation 1 = byte read or byte write operation (6:0) byte offset for byte read or byte write operations. for block read or block write operations, these bits should be ?0000000? table 3. block read and block write protocol block write protocol block read protocol bit description bit description 1start 1start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9write 9write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8-bit ?00000000? stands for block operation 11:18 command code ? 8-bit ?00000000? stands for block operation 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ?8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29:36 data byte 0 ? 8 bits 28 read 37 acknowledge from slave 29 acknowledge from slave 38:45 data byte 1 ? 8 bits 30:37 byte count from slave ? 8 bits 46 acknowledge from slave 38 acknowledge .... data byte n/slave acknowledge... 39:46 data byte from slave ? 8 bits .... data byte n ? 8 bits 47 acknowledge .... acknowledge from slave 48:55 data byte from slave ? 8 bits .... stop 56 acknowledge .... data bytes from slave/acknowledge .... data byte n from slave ? 8 bits .... not acknowledge .... stop table 4. byte read and byte write protocol byte write protocol byte read protocol bit description bit description 1 start 1 start 2:8 slave address ? 7 bits 2:8 slave address ? 7 bits 9 write 9 write 10 acknowledge from slave 10 acknowledge from slave 11:18 command code ? 8 bit ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 11:18 command code ? 8-bit ?1xxxxxxx? stands for byte operation bit[6:0] of the command code represents the offset of the byte to be accessed 19 acknowledge from slave 19 acknowledge from slave 20:27 byte count ? 8 bits 20 repeat start 28 acknowledge from slave 21:27 slave address ? 7 bits 29 stop 28 read 29 acknowledge from slave
cy28342 rev 1.0, november 20, 2006 page 6 of 21 since sdr and ddr zero delay buffers will share this same address, the device starts from byte 4. 30:37 data byte from slave ? 8 bits 38 not acknowledge 39 stop byte 4 : cpu clock register (all bits are read and write functional) bit @pup pin# name description 7 h/w setting 14 fs3 for selecting frequencies in table 1 . 6 h/w setting 4 fs2 for selecting frequencies in table 1 . 5 h/w setting 3 fs1 for selecting frequencies in table 1 . 4 h/w setting 2 fs0 for selecting frequencies in table 1 . 3 0 0 = hw, 1 = sw frequency selection. 2 h/w setting 15 fs4 for selecting frequencies in table 1 . 1 1 sscg spread spectrum enable . 0 = spread off, 1 = spread on. this is a read and write control bit. 0 0 master output control 0 = running, 1 = three-state all outputs. table 4. byte read and byte write protocol (continued) byte write protocol byte read protocol bit description bit description byte 5 : cpu clock register (all bits are read-only) bit @pup pin# name description 70 reserved. 60 reserved. 5 x 26 mult0 mult0 (pin 26) value. this bit is read-only. 4 x 15 fs4 fs4 read-back. this bit is read-only. 3 x 14 fs3 fs3 read-back. this bit is read-only. 2 x 4 fs2 fs2 read-back. this bit is read-only. 1 x 3 fs1 fs1 read-back. this bit is read-only. 0 x 2 fs0 fs0 read-back. this bit is read-only. byte 6 : cpu clock register (all bits are read and write functional) bit @pup pin# name description 7 0 function test bit. always program to 0. 6 0 reserved. 5 0 14 pci_f0 pci_stp# control of pci_f0. 0 = free running, 1 = stopped when pci_stp# is low. 4 0 15 pci_f1 pci_stp# control of pci_f1. 0 = free running, 1 = stopped when pci_stp# is low. 3 1 40,39 cpu0t/c controls cpu0t and cpu0c functionality when cpu_stp# is asserted low. 0 = free running, 1 = stopped with cpu_stp# asserted low. this is a read and write control bit. 2044,43cpu1t/c controls cpu1t and cpu1c functionality when cpu_stp# is asserted low 0= free running, 1 stopped with cpu_stp# asserted to low. this and read and write control bit. 1 1 40,39 cpu0t/c cpu0t, cpu0c output control, 1= enabled, 0 = disabled. this is a read and write control bit. 0144,43cpu1t/c cpu1t, cpu1c output control, 1= enabled, 0 = disabled. this is a read and write control bit.
cy28342 rev 1.0, november 20, 2006 page 7 of 21 byte 7 : pci clock register (all bits are read and write functional) bit @pup pin# name description 7 1 15 pci_f0 pci_f0 output control 1 = enabled, 0 = forced low. 6 1 14 pci_f1 pci_f1 output control 1 = enabled, 0 = forced low. 5 1 23 pci5 pci5 output control 1 = enabled, 0 = forced low. 4 1 22 pci4 pci4 output control 1 = enabled, 0 = forced low. 3 1 21 pci3 pci3 output control 1 = enabled, 0 = forced low. 2 1 20 pci2 pci2 output control 1 = enabled, 0 = forced low. 1 1 17 pci1 pci1 output control 1 = enabled, 0 = forced low. 0 1 16 pci0 pci0 output control 1 = enabled, 0 = forced low. byte 8 : silicon signature register (all bits are read-only) bit @pup description 7 1 vendor id 1000 = cypress 60 50 40 3 0 revision id 20 10 00 byte 9 : peripheral control register (all bits are read and write) bit @pup pin# name description 71 33 pd# pd# enable . 0 = enable, 1 = disable. 60 0 = when pd# asserted low, cpu(0:1)t stop in a high state, cpu(0:1)c stop in a low state. 1 = when pd# asserted low, cpu(0:1)t and cpu(0:1)c stop in h-z. 5 1 27 48m 48m output control 1 = enabled, 0 = forced low. 4 1 26 48m_24m 48m_24m output control 1 = enabled, 0 = forced low. 3 0 26 48m_24m 48m_24m, 0 = pin 26 output is 24mhz, 1= pin 28 output is 48 mhz. 2 0 ss2 spread spectrum control bit (0= down spread, 1= center spread). 1 0 ss1 spread spectrum control bit. see table 10. 0 0 ss0 spread spectrum control bit. see table 10. byte 10 : peripheral control register (all bits are read and write functional) bit @pup pin# name description 7 1 47 sdclk sdclk output enable 1 = enabled, 0 = disabled. 6 1 4 ref2 ref2 output control 1 = enabled, 0 = forced low. 5 1 3 ref1 ref1 output control 1 = enabled, 0 = forced low. 4 1 2 ref0 ref0 output control 1 = enabled, 0 = forced low. 3 1 10 zclk1 zclk1 output enable 1 = enabled, 0 = disabled. 2 1 9 zclk0 zclk0 output enabled 1 = enabled, 0 = disabled. 1 1 30 agp1 agp1 output enabled 1 = enabled, 0 = disabled. 0 1 31 agp0 agp0 output enabled 1 = enabled, 0 = disabled.
cy28342 rev 1.0, november 20, 2006 page 8 of 21 byte 11 : dial-a-skew? and dial-a-ratio? control register (all bits are read and write functional) bit @pup name description 7 0 darsd2 programming these bits allows modifying the frequency ratio of the sdclk clock relative to the vco. see table 5 . 6 0 darsd1 5 0 darsd0 4 0 darag2 programming these bits allows modifying the frequency ratio of the agp(1:0), pci(5:0) and pcif(0:1) clocks relative to the vco. see table 6 . 3 0 darag1 2 0 darag0 1 0 dassd1 programming these bits allows shifting skew between cpu and sdclk signals. see ta ble 7 . 0 0 dassd0 table 5. dial-a-ratio sdclk darsd (2:0) vc0/sdclk ratio 000 frequency selection default 001 2 010 3 011 4 100 5 101 6 110 8 111 9 table 6. dial-a-ratio agp(0:1) [3] darag (2:0) vc0/agp ratio 000 frequency selection default 001 6 010 7 011 8 100 9 101 10 110 10 111 10 table 7. dial-a-skew sdclk cpu dassd (1:0) sdclk-cpu skew 00 0 ps (default) [4] 01 +150 ps (cpu lag)* 10 +300 ps (cpu lag)* 11 +450 ps (cpu lag)* notes: 3. the ratio of agp to pci is retained at 2:1. 4. see figure 8 for cpu measurement point. see figure 9 for sdclk measurement point.
cy28342 rev 1.0, november 20, 2006 page 9 of 21 byte 12 : watchdog time stamp register (all bits are read and write functional) bit @pup name description 71 sreset#/pci_stp# . 1 = pin 12 is the input pin as pci_stp# signal. 0 = pin 12 is the output pin as sreset# signal. 60 frequency revert . this bit allows setting the revert frequency once the system is rebooted due to watchdog time-out only. 0 = selects frequency of existing h/w setting. 1 = selects frequency of the second to last s/w setting (the software se tting prior to the one that caused a system reboot). 50 wdtest . for wd-test, always program to ?0.? 40 wd alarm . this bit is set to ?1? when the watchdog times out. it is reset to ?0? when the system clears the wd time stamps (wd3:0). 3 0 wd3 these bits select the watchdog time stamp value. see table 8 . 20wd2 10wd1 00wd0 table 8. watchdog time stamp table wd(3:0) function 0000 off 0001 1 second 0010 2 seconds 0011 3 seconds 0100 4 seconds 0101 5 seconds 0110 6 seconds 0111 7 seconds 1000 8 seconds 1001 9 seconds 1010 10 seconds 1011 11 seconds 1100 12 seconds 1101 13 seconds 1110 14 seconds 1111 15 seconds byte 13 : dial-a-frequency control register n (all bits are read and write functional) [5] bit @pup description 7 0 reserved. 60n6, msb 50n5 40n4 30n3 20n2 10n3 00n0, lsb note: 5. byte 13 and byte 14 should be write together in every case.
cy28342 rev 1.0, november 20, 2006 page 10 of 21 dial-a-frequency feature smbus dial-a-frequency feature is available in this device via byte 13 and byte 14. p is a large-value, phase-locked loop (pll) constant that depends on the frequency selection achieved through the hardware selectors fs(4:0). p value may be determined from the following table. spread spectrum clock generation (sscg) spread spectrum is a modulation technique used to minimize electromagnetic interference (emi) radiation generated by repetitive digital signals. a clock presents the greatest emi energy at the center of the frequency it is generating. spread spectrum distributes this energy over a specific and controlled frequency bandwidth, thereby causing the average energy at any one point in this band to decrease in value. this technique is achieved by modulating the clock away from its resting frequency by a certain percentage (which also determines the amount of emi reduction). in this device, spread spectrum is enabled by setting specific register bits in the smbus control bytes. see the smbus register section of this data sheet for the exact bit and byte functionally. the following table is a listing of the modes and percentages of spread spectrum modulation that this device incorporates. byte 14 : dial-a-frequency control register (all bits are read and write functional) [5] bit @pup description 7 0 reserved. 60r5 msb 50r4 40r3 30r2 20r1 10r0, lsb 00 r and n register load gate . 0 = gate closed (data is latched), 1= gate open (data is loading from smbus registers into r and n)#. table 9. fs(4:0) p 00000, 00001, 00010, 00111, 01001, 01011, 01110, 01111, 10 010, 10100, 10110 95996900 00100, 00101, 10000, 10001, 10101, 10111, 11000, 11010, 11100, 11101, 11110, 11111 76797520 00110, 01000, 01010, 01100, 01101, 11001, 11011 63997933 00011, 10011 127995867 table 10.spread spectrum ss2 ss1 ss0 spread mode spread% 0 0 0 down 0, ?0.50 0 0 1 down +0.12, ?0.62 0 1 0 down +0.25, ?0.75 0 1 1 down +0.50, ?1.00 1 0 0 center +0.25, ?0.25 1 0 1 center +0.37, ?0.37 1 1 0 center +0.50, ?0.50 1 1 1 center +0.75, ?0.75
cy28342 rev 1.0, november 20, 2006 page 11 of 21 system self-recovery clock management this feature is designed to allow the system designer to change frequency while the system is running and reboot the operation of the system in case of a hang up due to the frequency change. when the system sends an smbus command requesting a frequency change through byte 4 or through bytes 13 and 14, it must have previously sent a command selecting which time-out stamp the watchdog must perform to byte 12, or the system self-recovery feature will not be applicable. conse- quently this device will change frequency, and then the watchdog timer starts timing. meanwhile, the system bios is running its operation with the new frequency. if this device receives a new smbus command to clear the bits originally programmed in byte 12, bits(3:0) (reprogram to 0000) before watchdog times out, this device will keep operating in its normal condition with the new selected frequency. if the watchdog times out the first time before the new smbus repro- grams byte 12, bits(3:0) to (0000), then this device will send a low system reset pulse, on sreset# (see byte 12, bit 7), and changes the watchdog alarm (byte 12, bit 4) status to ?1? then restarts the watchdog timer. if the watchdog times out a second time, this device will send another low pulse on sreset#, will relatch original hardware strapping frequency (or second-to-last software-selected frequency, see byte 12, bit6) selection, set watchdog alarm bit (byte 12, bit4) to ?1,? then start the watchdog timer again. the above-described sequence will keep repeating until the bios clears the smbus byte 12 bits(3:0). once the bios sets byte 12 bits(3:0) = 0000, the watchdog timer is turned off and the watchdog alarm bit (byte 12, bit 4) is reset to ?0.? system running with o rig in a lly s e le c te d frequency via hardware strapping. receive frequency change request via sm bus byte 4 or via dial- a-frequency? start internal watch dog tim er. w atch dog tim e out? turn off watch dog tim er. keep new frequency setting. set w d alarm bit (byte 12, bit4) to ''0' 1) send another 3m s low pulse on sreset 2) relatch original hardware strapping selection for return to original frequency settings. 3) set w d alarm bit (byte 12, bit4) to "1" 4 ) s ta rt w d tim e r frequency will change but system self recovery not applicable (no tim e stam p selected and byte 12, bit(3:0) is still = "0000" no no yes no no yes sm bus byte 12 tim e out stam p disabled? is smbus byte 9, tim e out stam p enabled - (byte 12, bit (3:0) 0000)? change to a new frequency yes 1) send sreset pulse 2) set w d bit (byte12, bit4) to '1' 3) start w d tim er yes w atch dog tim e out? no yes smbus byte 9 tim e out stam p disabled, byte 12, bit(3:0) = (0000)? yes no table 11.cpu clock current select function mult0 board target trace/term z reference r, iref ? v dd (3*rr) output current voh @ z 0 50 ohms (not used) rr = 221 1%, iref = 5.00ma i oh = 4*iref 1.0v @ 50 1 50 ohms rr = 475 1%, iref = 2.32ma i oh = 6*iref 0.7v @ 50 table 12.group timing relation ship and tolerances offset tolerance(or range) conditions notes cpu to sdclk typical 0 ns 2 ns cpu leads note 6 cpu to agp typical 2 ns 1-4ns cpu leads note 6 cpu to zclk typical 2 ns 1-4ns cpu leads note 6 cpu to pci typical 2 ns 1-4ns cpu leads note 6
cy28342 rev 1.0, november 20, 2006 page 12 of 21 note: 6. see figure 8 for cpu clock-measurement point. see figure 9 for sdclk, agp, zclk and pci output-measurement points. table 12.group timing relation ship and tolerances
cy28342 rev 1.0, november 20, 2006 page 13 of 21 cpu_stp# clarification the cpu_stp# signal is an active low input used for synchronous stopping and starting of the cpu output clocks while the rest of the clock generator continues to function. cpu_stp# assertion when cpu_stp# pin is asserted, all cpu outputs that are set with the smbus configuration to be stoppable via assertion of cpu_stp# will be stopped after being sampled by two falling cpu clock edges. the final state of the stopped cpu signals is cpu = high and cpu0# = low. there is no change to the output drive current values during the stopped state. the cpu is driven high with a current value equal to (mult0 ?select?) (iref), and the cpu# signal will not be driven. due to external pull-down circuitry, cpu# will be low during this stopped state. cpu_stp# deassertion the deassertion of the cpu_stp# signal will cause all cpu outputs that were stopped to resume normal operation in a synchronous manner. synchronous manner meaning that no short or stretched clock pulses will be produce when the clock resumes. the maximum latency from the deassertion to active outputs is no more than two cpu clock cycles. cpu_stp# cput cpuc figure 1. assertion cpu_stp# waveform cpu_stp# cput cpuc cput cpuc figure 2. deassertion cpu_stp# waveform
cy28342 rev 1.0, november 20, 2006 page 14 of 21 pci_stp# assertion the pci_stp# signal is an active low input used for synchronous stopping and starting the pci outputs while the rest of the clock generator continues to function. the set-up time for capturing pci_stp# going low is 10 ns (t setup ). (see figure 3 .) the pci_f (0:2) clocks will not be affected by this pin if their control bits in the smbus register are set to allow them to be free running. pci_stp# deassertion the deassertion of the pci_stp# signal will cause all pci(0:6) and stoppable pci_f(0:2) clocks to resume running in a synchronous manner within two pci clock periods after pci_stp# transitions to a high level. note: 7. the pci stop function is controlled by 2 inputs. one is the device pci_stp# pin number 34 and the other is smbus byte 0 bit 3 . these 2 inputs are logically anded. if either the external pin or the internal smbus register bit is set low then the stoppable pci clocks will be stopped i n a logic low state. reading smbus byte 0 bit 3 will return a 0 value if either of these control bits are set low thereby indicating the device?s stoppable pci cl ocks are not running. pci_stp# pci_f(0:2) 33m pci(0:6) 33m setup t figure 3. assertion pci_stp# waveform pci_stp# pci_f(0:2) pci(0:6) setup t figure 4. deassertion pci_stp# waveform [7]
cy28342 rev 1.0, november 20, 2006 page 15 of 21 pd# (power-down) clarification the pd# (power-down) pin is used to shut off all clocks prior to shutting off power to the device. pd# is an asynchronous active low input. this signal is synchronized internally to the device powering down the clock synthesizer. pd# is an asynchronous function for powering up the system. when pd# is low, all clocks are driven to a low value and held there and the vco and plls are also powered down. all clocks are shut down in a synchronous manner so has not to cause glitches while transitioning to the low ?stopped? state. pd# - assertion (transition from logic ?l? to logic ?0?) when pd# is sampled low by two consecutive rising edges of cpuc clock then all clock outputs (except cput) clocks must be held low on their next high-to-low transition. cput clocks must be hold with cput clock pin driven high with a value of 2x iref and cpuc undriven. due to the state of the internal logic, stopping and holding the ref clock outputs in the low state may require more than one clock cycle to complete. pd# deassertion (transition fro m logic ?0? to logic ?1?) the power-up latency between pd# rising to a valid logic ?1? level and the starting of all clocks is less than 3.0 ms. note: 8. device is not affected; vttpwrgd is ignored. pd# cpu(0:1)t cpu(0:1)c cpu internal cpu# internal figure 5. power-down assertion/deassertion timing waveforms ? nonbuffered mode vid (0:3), sel (0,1) vttpwrgd pwrgd vdd clock gen clock state clock outputs clock vco 0.2-0.3ms delay state 0 state 2 state 3 wait for vtt_gd# sample sels off off on on state 1 (note a) figure 6. vttpwrgd timing diagram [8]
cy28342 rev 1.0, november 20, 2006 page 16 of 21 v t t p w r g d = h i g h delay 0.25ms s1 power off s0 vdda = 2.0v sample inputs fs(3:0) s2 vdd3.3 = off normal operation s3 wait for 1.146ms enable outputes outputs figure 7. clock generator power-up/run state diagram
cy28342 rev 1.0, november 20, 2006 page 17 of 21 maximum ratings input voltage relative to v ss ................................v ss ? 0.3v input voltage relative to v ddq or av dd : ............. v dd + 0.3v storage temperature:..................................?65 q c to +150 q c operating temperature: ....................................0 q c to +70 q c maximum power supply: ............. .............. .............. ...... 3.5v dc characteristics current accuracy [9] conditions configuration load min. max. iout v dd = nominal (3.30v) m0= 0 or 1 and rr shown in table nominal test load for given configuration ?7% inom +7% inom iout v dd = 3.30 5% all combinations of m0 or 1 and rr shown in table nominal test load for given configuration ?12% inom +12% inom dc component parameters (v dd =3.3v5%, ta = 0c to 70c) parameter description min. typ. max. units conditions idd3.3v dynamic supply current 280 ma all frequencies at maximum values [10] ipd3.3v power-down supply current note 11 ma pd# asserted cin input pin capacitance 5 pf cout output pin capacitance 6 pf lpin pin inductance 7 nh cxtal crystal pin capacitance 30 36 42 pf measured from the x in or x out pin to ground ac parameters parameter description 100 mhz 133 mhz unit notes min. max. min. max. crystal tdc x in duty cycle 47.5 52.5 47.5 52.5 % 12,13 tperiod x in period 69.841 71.0 69.841 71.0 ns 12,13,14,15 vhigh x in high voltage 0.7v dd v dd 0.7v dd v dd v vlow x in low voltage 0 0.3v dd 00.3v dd v tr/tf x in rise and fall times 10.0 10.0 ns tccj x in cycle to cycle jitter 500 500 ps 13,14,16 cpu at 0.7v timing tskew any cpu to cpu clock skew 150 150 ps 16, 17, 18 tccj cpu cycle to cycle jitter 150 150 ps 16, 17, 18 tdc cpu and cpuc duty cycle 45 55 45 55 % 16, 17, 18 tperiod cpu and cpuc period 9.8 10.2 7.35 7.65 ns 16, 17, 18 notes: 9. inom refers to the expected current based on the configuration of the device. 10. all outputs loaded as per maximum capacitive load table. 11. absolute value = (programmed cpu iref 97) +10 ma. 12. this parameter is measured as an average over 1 p s duration with a crystal center frequency of 14.318 mhz. 13. when x in is driven from an external clock source. 14. all outputs loaded per table 13 below. 15. probes are placed on pins and measurements are acquired at 1.5v for 3.3v signals (see test and measurement set-up section). 16. this measurement is applicable with spread on or spread off. 17. measured at crossing point (vx), or where subtraction of clk?clk# crosses 0v. 18. for cpu load. see figure 8 .
cy28342 rev 1.0, november 20, 2006 page 18 of 21 tr/tf cpu and cpuc rise and fall times 175 700 175 700 ps 16,19 rise/fall matching 20% 20% 18,19,20 deltatr rise time variation 125 125 ps 18,19 deltatf fall time variation 125 125 ps 18,19 vcross crossing point voltage at 0.7v swing 280 430 280 430 mv 17,18,19 agp tdc agp duty cycle 45554555 % 14, 15 tperiod agp period 15.0 15.3 15.0 15.3 ns 14, 15 thigh agp high time 5.25 5.25 ns 21 tlow agp low time 5.05 5.05 ns 22 tr/tf agp rise and fall times 0.5 1.6 0.5 1.6 ns 14, 23 tskew unbuffered any agp to any agp clock skew 175 175 ps 14, 15 tccj agp cycle-to-cycle jitter 250 250 ps 14, 15 zclk tdc zclk(0:1) duty cycle 45 55 45 55 % 14, 15 tr/tf zclk(0:1) rise and fall times 0.5 1.6 0.5 1.6 ns 14, 23 tskew any zclk(0:1) to any zclk(0:1) skew 175 175 ps 14, 15 tccj zclk(0:1) cycle-to-cycle jitter 250 250 ps 14,15 pci tdc pci_f(0:1) pci (0:5) duty cycle 45 55 45 55 % 14, 15 tperiod pci_f(0:1) pci (0:5) period 30.0 30.0 ns 12,14,15 thigh pci_f(0:1) pci (0:5) high time 12.0 12.0 ns 21 tlow pci_f(0:1) pci (0:5) low time 12.0 12.0 ns 22 tr/tf pci_f(0:1) pci (0:5) rise and fall times 0.5 2.0 0.5 2.0 ns 14, 23 tskew any pci clock to any pci clock skew 500 500 ps 14, 15 tccj pci_f(0:1) pci (0:5) cycle-to-cycle jitter 250 250 ps 14, 15 sdclk tdc sdclk duty cycle 45 55 45 55 % 14, 15 tperiod sdclk period 9.8 10.2 7.35 7.65 ns 14, 15 thigh sdclk high time 3.0 1.87 ns 21 tlow sdclk low time 2.8 1.67 ns 22 tr/tf sdclk rise and fall times 0.4 1.6 0.4 1.6 ns 14, 23 tccj sdclk cycle-to-cycle jitter ? 250 ? 250 ps 14, 23 48m tdc 48m duty cycle 45 55 45 55 % 14, 15 tperiod 48m period 20.829 20.834 20.829 20.834 ns 14, 15 tr/tf 48m rise and fall times 1.0 2.0 1.0 2.0 ns 14, 23 tccj 48m cycle-to-cycle jitter 350 350 ps 14, 15 notes: 19. measured from v ol = 0.175 to v oh = 0.525v. 20. determined as a fraction of 2*(trise?tfall)/(trise+tfall). 21. thigh is measured at 2.4v for all non-host outputs. 22. tlow is measured at 0.4v for all non-host outputs. 23. probes are placed on pins and measurements are acquired between 0.4v and 2.4v for 3.3v signals (see test and measurement set -up section). ac parameters (continued) parameter description 100 mhz 133 mhz unit notes min. max. min. max.
cy28342 rev 1.0, november 20, 2006 page 19 of 21 24m tdc 24-mhz duty cycle 45554555 % 14, 15 tperiod 24-mhz period 41.66 41.67 41.66 41.67 ns 14, 15 tr/tf 24-mhz rise and fall times 1.0 4.0 1.0 4.0 ns 14, 23 tccj 24-mhz cycle-to-cycle jitter 500 500 ps 14, 15 ref tdc ref duty cycle 45554555 % 14, 15 tperiod ref period 69.8413 71.0 69.8413 71.0 ns 14, 15 tr/tf ref rise and fall times 1.0 4.0 1.0 4.0 ns 14, 23 tccj ref cycle-to-cycle jitter 1000 1000 ps 14, 15 enable/disable and set up tpzl, tpzh output enable delay (all outputs) 1.0 10.0 1.0 10.0 ns tplz, tpzh output disable delay (all outputs) 1.0 10.0 1.0 10.0 ns tstable all clock stabilization from power-up 1.5 1.5 ms tss stopclock set-up time 10.0 10.0 ns tsh stopclock hold time 0 0 ns 24 ac parameters (continued) parameter description 100 mhz 133 mhz unit notes min. max. min. max. table 13.maximum lumped capacitive output loads clock max. load units pci(0:5), pci_f(0:1) 30 pf agp (0:1), sdclk 30 pf zclk (0:1) 30 pf 48m_24, 48m clock 20 pf ref (0:2) 30 pf cpu(0:1)t cpu(0:1) c 2pf notes: 24. cpu_stp# and pci_stp# set-up time with respect to any pci_f clock to guarantee that the affected clock will stop or start at the next pci_f clock?s rising edge. 25. when crystal meets minimum 40 ohm device series resistance specification. 26. this is required for the duty cycle on the ref clock out to be as specified. the device will operate reliably with input dut y cycles up to 30/70, but the ref clock duty cycle will not be within data sheet specifications.
cy28342 rev 1.0, november 20, 2006 page 20 of 21 test and measurement set-up for differential cpu output signals the following diagram shows lumped test load configurations for the differential host clock outputs. cput multsel t pcb t pcb cpuc 33 : 33 : 49.9 : 49.9 : measurement point 2 pf 475 : iref measurement point 2 pf figure 8. 0.7v configuration 2.4v 0.4v 3.3v 0v tr tf 1.5v 3.3v signals td c probe output under test load cap - - figure 9. lumped load fo r single-ended output signals (for ac parameters measurement) ordering information part number package type product flow cy28342oc 48-pin shrunk small outline package (ssop) commercial 0 q to 70 q c CY28342OCT 48-pin shrunk small outline package (ssop) ? tape and reel commercial 0 q to 70 q c cy28342zc 48-pin thin shrunk small outline package (tssop) commercial 0 q to 70 q c cy28342zct 48-pin thin shrunk small outline package (tssop) ? tape and reel commercial 0 q to 70 q c
rev 1.0, november 20, 2006 page 21 of 21 cy28342 while sli has reviewed all information herein for accuracy and reliability, spectra linear inc. assumes no responsibility for t he use of any cir- cuitry or for the infringement of any patents or other rights of third parties which would result from each use. this product i s intended for use in normal commercial applications and is not warranted nor is it intended for use in life support, critical medical instruments, o r any other applica- tion requiring extended temperature range, high reliability, or any other extraordinary environmental requirements unless pursu ant to additional processing by spectra linear inc., and expressed written agreement by spectra linear inc. spectra linear inc. reserves the righ t to change any circuitry or specification without notice. package drawing and dimensions 48-lead shrunk small outline package o48 48-lead thin shrunk small outline package, type ii (6 mm x 12 mm) z48 51 85059 *b

▲Up To Search▲

Price & Availability of CY28342OCT

	To Download CY28342OCT Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .